PLL frequency synthesizer with K multiplication in addition to division for subtraction of phase noise

ABSTRACT

A frequency synthesizer is supplied with an input signal of frequency ƒ i  to provide an output signal ƒ o  where ƒ o= ƒ i  M/N and M and N are integers. The input signal is first applied to a divider circuit for division by M/K where K is an integer and the resultant is applied as inputs to a phase locked loop. The phase locked loop includes a ring oscillator of frequency ƒ i  N/M, a frequency multiplier circuit for multiplying by K, and a frequency divider circuit for dividing by N. The ring oscillator uses a combinational logic circuit that combines the outputs of four differential delay elements to produce a frequency multiplication of four.

FIELD OF THE INVENTION

This invention relates to frequency synthesizers and more particularlyto frequency synthesizers that use a phase-locked loop to generate theoutput frequency.

BACKGROUND OF THE INVENTION

A frequency synthesizer is a circuit that generates one or more outputsignals whose frequency bears a prescribed relation to the frequency ofan input reference signal. Such circuits are used as accurate frequencysources in a wide variety of electronic apparatus.

Generally a frequency synthesizer provides an output frequency ##EQU1##where ƒ_(i) is the input or reference frequency and where the values ofN and M are integers chosen to provide the desired ratio between theinput and output frequencies.

A common form of frequency synthesizer uses a phase-locked loop (PLL) toset the output frequency. In FIG. 1 there is shown the basic circuit 10of a common form of prior art PLL frequency synthesizer. A signal offrequency ƒ_(i) is supplied as an input to a divider circuit 12. Theoutput of the divider circuit is supplied as an input to the PLL 14, anelement of which is a divider circuit. For purposes of illustration, thedivider circuit has been shown as a separate element 16 in the feedbackloop of the PLL, although more precisely it can be viewed to be a partof the PLL. An expanded view of a PLL is shown in FIG. 3. As shown inFIG. 1, the divider 12 divides by the integer M and the divider 16 bythe integer N. The signal of output frequency ƒ_(o) from the PLL has afrequency of ƒ_(i) N/M.

The principles of PLL frequency synthesizers are set forth in a bookentitled Phase-Locked Loop Circuit Design by D. H. Wolaver,Prentice-Hall, Englewood Cliffs, N.J., (1991) with particular referenceto Chapter 11, pages 239-260, "Frequency Synthesizers" and the teachingsof the book are incorporated herein by reference.

A PLL generally comprises a closed loop that includes a phase detector(PD) and a voltage controlled oscillator (VCO), along with a frequencydivider that divides by N. When in lock, the frequency ƒ_(i) /M and thefrequency ƒ_(o) /N that serve as frequencies of the two inputs to thephase detector are equal, so that the output frequency ƒ_(o) is equal toƒ_(i) N/M. A common form of VCO for use in a PLL is a ring oscillatorthat employs a series of delay elements to provide the desired frequencyrange of operation.

The bandwidth of the closed loop is known to be an important factor incontrolling the jitter in the output frequency of a PLL frequencysynthesizer. In particular, a wide loop bandwidth can offer a highersuppression of the VCO phase noise than a narrow loop bandwidth.Quantitatively the output jitter is inversely proportional to the squareroot of the loop bandwidth. However loop stability considerations limitthe closed loop bandwidth that can be safely used. The limit is about atenth of the rate at which the PD in the PLL is updating. Thus large Mand/or N values in the PLL shown in FIG. 1 restrict the feasiblebandwidth of the loop.

The present invention seeks to avoid this problem and makes it feasibleto employ relatively large values of M and/or N defining the relationbetween the input and output frequencies without violating loopstability considerations.

SUMMARY OF THE INVENTION

In accordance with the invention, a PLL frequency synthesizer that isdesigned to provide an output frequency ƒ_(o) =N/Mƒ_(i) uses a firstfrequency divider to divide the input signal to the PLL by a factor ofM/K (where M/K is an integer) and then includes in the loop of the PLLboth a circuit for dividing by N and a circuit for multiplying by thefactor K. The factors K and M/K are each appropriately chosen integers,as will be discussed below. In this instance because the input frequencyto the PLL has been increased by the factor K, the bandwidth feasiblefor the loop is multiplied by the factor K. The larger bandwidth for theloop provides higher suppression of the VCO phase noise and betterjitter control of the output frequency of the frequency synthesizer.

Moreover, in a preferred product embodiment of the invention, in thering oscillator structure of the VCO, as a separate feature of theinvention, a logic circuit combines the outputs of the delay elements inthe ring to realize a clock output of the VCO that is K times the basicVCO frequency. In particular in an illustrative embodiment, K is chosento be four, and four delay elements are used in the ring of the VCO toproduce eight equally spaced phases that are combined in a novelcombinational logic circuit to realize a clock that is four times thebasic VCO frequency.

In accordance with a process embodiment, the invention is a method inwhich an output signal of frequency ƒ_(i) N/M is synthesized from aninput signal of frequency ƒ_(i) and where M and N are integers. Themethod is as follows: An input signal of frequency ƒ_(i) has itsfrequency divided to provide a resulting frequency of ƒ_(i) K/M where Kand K/M are integers; the resultant is applied as one input to the phasedetector of a phase locked loop and the output of the phase detector isused to control an oscillator in the phase locked loop; a portion of theoscillator output that has a frequency ƒ_(i) N/M, has its frequencymultiplied by K and divided by N to provide a signal that is used as thesecond input to the phase detector of the phase locked loop.

The invention will be better understood when taken with the followingmore detailed description.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a block diagram of the basic PLL frequency synthesizer of theprior art that has been discussed.

FIG. 2 is a block diagram of a PLL frequency synthesizer in accordancewith the invention.

FIG. 3 is a block circuit schematic of the frequency synthesizer of FIG.2.

FIG. 4 is a block circuit schematic of a preferred form of avoltage-controlled; ring oscillator for use in the frequency synthesizerof FIG. 3.

FIG. 5 illustrates the wave forms produced by the ring oscillator shownin FIG. 4.

FIG. 6 illustrates the logic circuit for combining the eight wave formsof FIG. 4 to provide a clock that is four times the basic frequency ofthe VCO in accordance with a feature of the preferred embodiment of theinvention.

DETAILED DESCRIPTION

With reference now to FIG. 2, the PLL frequency synthesizer 20 is anillustrative embodiment of the invention that is designed specificallyto convert an input signal of frequency ƒ_(i) of 51.84 MHz to an outputsignal of frequency ƒ_(o) of 29.16 MHz, a reduction by a factor of 9/16(N=9, M=16). To this end, the synthesizer 20 includes a circuit 22 thatdivides the input frequency by a factor M/K. This signal is supplied asone signal to the PLL 24. The value of K in the example is four. The PLLincludes in its closed loop 25 a circuit 28 that multiplies thefrequency of the VCO by the factor K, and a circuit 26 that divides thefrequency of its input signal by N, nine in this example. Accordingly,the closed loop essentially provides a division by 9/4. The net effectof the circuit 20 is to provide a factor of 9/16 for N/M in equation(1).

FIG. 3 is a more detailed circuit block schematic of a preferredembodiment 30 of the invention. In some respects, circuit 30 resemblesthe frequency synthesizer described in my prior U.S. Pat. No. 5,565,817that issued on Oct. 15, 1996. It includes a phase detector 32 (PD) whoseoutput supplies a charge pump 33 that supplies a loop filter 34. Theloop filter output is applied as an input to a voltage controlled ringoscillator 35 (VCO). The output of the VCO is the useful output offrequency ƒ_(o). A portion of this output is supplied to a novel circuit36, described as "a phase combining multiplier," to be discussed in moredetail with respect to FIGS. 4 and 5. Circuit 36 multiplies thefrequency ƒ_(o) by a factor K, for example 4, in the specificillustrative embodiment.

The output of circuit 36 is applied as an input to the frequency dividercircuit 37, which divides the multiplied frequency Kƒ_(o) by N toprovide a signal of frequency ƒ_(o) K/N that is applied as one input ofthe phase detector 32. The other input of the phase detector that needsto lock with the first input is a signal of frequency ƒ_(i) M/K obtainedby dividing the input reference signal of frequency ƒ_(i) by M/K individer circuit 39. The values of M and N are chosen to provide thedesired relationship ƒ_(o) =M/Nƒ_(i). In the illustrative embodimentsƒ_(i) is 51.84 MHz and ƒ_(o) 29.16 MHz and the smallest set of M and Nintegral values to achieve the desired frequency change is M equal to 16and N equal to 9.

The basic operation of a frequency synthesizer of the general typerepresented by FIG. 3 is described in detail in my prior aforementionedpatent whose disclosure is incorporated herein by reference.

FIG. 4 shows the basic structure of a voltage controlled ring oscillatorsuitable for use in the circuit of FIG. 3. It comprises a ring of fouruniform stages of differential delay elements 41-44, such as isdescribed in the aforementioned patent. The current through the delayelements, which is controlled by a control voltage, sets the delay ofthe delay elements. The outputs of the four stages are provided witheight taps P₁ -P₈ as shown. When the loop is in lock, the eight taps ofthe fully differential four stage ring oscillator produce eight equallyspaced phases, as seen in FIG. 5, where there is shown plotted versustime the wave forms 51-58 available at the eight different taps P₁ -P₈.

To provide the desired multiplication by a factor of four, the eightdifferent waveforms are combined in the manner shown in FIG. 6 by theuse of four two-input NAND gates 61-64 and the single four-input NANDgate 65. In particular, the waveforms at taps P₆ and P₁ are combined inNAND 61, P₈ and P₃ in NAND 62, P₂ and P₅ in NAND 63, P₄ and P₈ in NAND64. The outputs of the four NANDs 61-64 are combined in NAND 65. In FIG.5, the resultant waveform of the combinational logic operation P₁ P₆ +P₃P₈ +P₅ P₂ +P₇ P₄ is shown as waveform 59. It can be appreciated that byappropriate choice of the number of delay elements in the ringoscillator and appropriate combinations of the different waveformsavailable the multiplication factor can be controlled to a desiredvalue. It should be noted that NAND gate 65 should have essentially thesame delay from each of its four inputs to its output.

The arrangement of FIG. 6 when combined with a voltage-controlled ringoscillator of the kind shown in FIG. 4 can provide a signal of frequency4ƒ_(o) to the divider 37 in the frequency synthesizer of FIG. 3.

Accordingly, it can be appreciated that the invention makes possible awide range of frequency conversions by appropriate choice of values of Mand N and by appropriate choice of the K factor. Relatively large valuesof M and N can be used while still providing a wide enough bandwidth inthe closed loop of the PLL to keep jitter low in the synthesizedfrequency. Specifically the bandwidth of the loop can be increased bythe value of K as compared to the prior art.

Accordingly, it is to be understood that the specific embodimentdescribed is merely illustrative of the general principles of theinvention and various other embodiments may be devised without departingfrom the spirit and scope of the invention.

What is claimed:
 1. A frequency synthesizer for converting an inputsignal of frequency ƒ_(i) applied to its input terminal to an outputsignal of frequency ƒ_(o) at its output terminal where ƒ_(o) =N/Mƒ_(i)where N and M are integers comprising a first divider circuit forreceiving the input signal of frequency ƒ_(i) and providing a signal offrequency ƒ_(i) K/M where K and K/M are integers;a phase detector havinga first and second input terminal and an output terminal, the firstinput terminal of the phase detector being supplied with a first signalof frequency ƒ_(i) K/M; a phase-locked loop between said second inputterminal of the phase detector and the output of the phase locked loop,the loop including a voltage controlled oscillator for operating atƒ_(o), a circuit for multiplying by K and a circuit for dividing by Nfor providing a signal of ƒ_(o) K/N to the second input terminal of thephase detector; the output terminal of the voltage-controlled oscillatorbeing the output of the synthesizer.
 2. A frequency synthesizer inaccordance with claim 1 in which M equals 16, N equals 9, and K equals4.
 3. A frequency synthesizer in accordance with claim 1 in which thevoltage controlled oscillator is (the) a ring oscillator that includesfour differential delay elements whose eight terminals provide eightsignals of different phases and the multiplier circuit for multiplyingby K includes four two-input NAND gates, each of which is supplied asinputs with a different pair of the eight signals and whose four outputsare supplied to a four-input NAND gate whose output is supplied to the(second divider) circuit for dividing by N.
 4. A frequency synthesizerin accordance with claim 1 in which N is smaller than M whereby theoutput frequency is a fraction of the input frequency.
 5. A process forsynthesizing an output signal of frequency _(o) from an input signal offrequency ƒ_(i) where ƒ_(o) N/M where N and M are integers comprisingthe steps ofproviding from the input signal a signal of frequency ƒ_(i)K/M where K and M/K are integers; applying this signal of frequencyƒ_(i) K/M as one input to a phase detector of a phase-locked loop thatincludes a voltage-controlled oscillator; providing as the second inputto the phase detector a signal of frequency ƒ_(o) K/N obtained bymultiplying by K and dividing by N the frequency ƒ_(o) available at theoutput terminal of the voltage-controlled oscillator of the phase-lockedloop; using the output of the phase detector to control the frequency ofthe voltage-controlled oscillator in the phase-locked loop so that itsoutput is a signal of the desired output frequency ##EQU2##
 6. Theprocess of claim 5 in which the voltage-controlled oscillator is a ringoscillator comprising four delay elements in a ring and the delayelements are used to create eight equally spaced pulses that arecombined in turn in four two-input NAND circuits whose outputs arecombined in a four-input NAND circuit to provide an output that is 4times the voltage controlled oscillator frequency for use in providingthe second input.
 7. A circuit for multiplying by four the outputfrequency of a voltage-controlled oscillator that includes as itsfeedback path a ring of four uniform stages of differential delayelements comprising: eight taps, a different one at each of the eightterminals associated with the four stages of delay elements;fourtwo-input NAND circuits each supplied with the voltages at a differentpair of taps from two different delay elements, and providing a separateoutput; and a four-input NAND circuit to which are supplied as inputsthe separate outputs of said four two-input NAND circuits for providingat its output the multiplied-by-four frequency.